1. Field of the Invention
The present invention relates in general to an integrated circuit tester employing a pattern generator to control activities of a pin electronics circuit during a test, and in particular to a tester using the pattern generator to also provide on-the-fly adjustment of test parameters before or during the test.
2. Description of Related Art
A typical integrated circuit (IC) tester includes a set of tester channels, one for each pin of an integrated circuit device under test (DUT). During each cycle of a test, each channel can either supply a digital test signal to the pin or monitor a DUT output signal produced at the pin to determine whether the DUT is behaving as expected during the test cycle. At the start of each test cycle, a large central pattern generator provides input channel data concurrently to all channels defining an action or actions to be taken at the DUT terminal during the test cycle. The channel data typically includes "format set" (FSET) data indicating the action or actions to be taken during the test cycle and "time set" (TSET) data indicating a time or times during the test cycle at which the action is to be taken. When a channel is monitoring a DUT output signal during the test cycle a data value (PG) usually indicates the expected state or states of the DUT output signal. When the channel is to supply a test signal to the DUT terminal the PG data can be used with the FSET data to provide additional bits for selecting the format of the test signal.
A pattern generator typically includes an addressable pattern memory for storing at each address all of the channel control data needed for one cycle of the test. A counter or sequencer within the pattern generator sequentially addresses the pattern memory during the test so that it reads out the pattern data for each cycle of the test. The pattern memory is connected to a host computer via a conventional computer bus so that the host computer can write pattern data provided by a user into the pattern memory before the test.
The host computer also uses that bus to write control data into addressable storage locations within various tester components other than the pattern memory. This control data adjusts test parameters to meet the requirements of the test to be performed. For example, since DUTs operate at various logic levels, testers typically allow the host computer to adjust test signal logic levels. Since DUTs operate at various supply voltages levels, a tester allows the host computer to adjust the DUT power supply voltage. Also in some systems the host computer can adjust the manner in which each tester channel responds to various combinations of values of FSET, TSET and PG channel data during a test by writing control data to memories within the tester channels controlling how the channels decode the FSET, TSET and PG data into signals that actually control channel activities during the cycle.
Logic tests are often performed repeatedly on a DUT with operating parameters being changed before each repetition. For example if a DUT is rated as being operable with a supply voltage of 3 to 5 volts, DUT logic can be repeatedly tested at several different supply voltages between 3 and 5 volts to ensure that the DUT operates properly over its entire supply voltage range. Or if a DUT is supposed to respond to test signals having logic levels within a specified range, a logic test can be repeatedly performed at several logic levels within that range. Thus after each logic test a host computer must write new control data into the tester to adjust its operating parameters and then signal the pattern memory to repeat the logic test.
Some testers can also perform other tests in addition to digital logic tests. For example a tester may also perform a leakage current test to determine whether DUT leakage current is within an acceptable range or may be able to directly measure leakage current. In these testers a host computer can, for example after having the tester perform a digital logic test on a DUT, send control data configuring the tester to perform a leakage current test on the same DUT and then initiate a leakage current test.
Thus a prior art tester can perform a series of tests on a DUT. But to do so the host computer must wait for the pattern generator to signal that it has completed one test of a series, check the results of the test, write new control data to the tester to configure it for the next test, reprogram the pattern generator for the next test, and then signal the pattern generator to restart. This process is relatively slow. It would be desirable if a tester could carry out a series of tests requiring reconfiguration of the tester between or during tests, but without requiring the host computer to check test results or reprogram the pattern generator between tests.